The Maestro CD Player is not based on the development of pre-existing projects such as the other components of the SE line but has been totally built from scratch instead.
The Maestro CD player reduces jitter problems thanks to an innovative piece of technology entirely developed by Audio Analogue. The technology uses a ”discrete components” PLL to lock the digital signal. The whole chain can reach 192 KHz/24bits and a new previously unseen fully differential low noise configuration has been used in the output stage.
The excellence of the player is made complete by:
- The extreme flexibility which allows the user to set many parameters of the DA conversion such as the sampling frequency.
- The digital input which allows the user to use the unit as a DA converter from a digital source with a sampling frequency of up to 192 KHz.
It’s possible to select three different modes:
Direct Mode – The SPDIF RX receives the selected digital signal which is then directly sent to the DAC. In this mode there is no up-sampling so the sample frequency remains the same along the chain until the DAC, both when the signal from the CD Mechanism is selected and when the signal from the SPDIF IN is selected.
PLL Mode – This mode is available only when the selected digital signal is the one coming from the CD mechanism. The system clock from the SPDIF RX is sent to the PLL, which, if it can lock to it, regenerates and cleans it reducing the jitter for frequencies higher than 20Hz (according to a second order filter). This improved clock is then used to “re-synchronize” all the signals inside the CPLD. If the signals from the CPLD are then directly sent to the DAC, it will work just at 44.1KHz as sample frequency, while if the SRC is enabled the sample frequency can be increased by a factor of 1X, 2X or 4X. Such information is shown on the display by: SRCX1, SRCX2, SRCX4. The sample rate converter factor like all the other parameters can be set in the PLL mode menu option
SRC Mode – The signals from the SPDIF RX are sent directly to the SRC and from this to the DAC. The SRC re-synchronize the signals with an external reference clock reducing the Jitter to an extremely low level. In fact, the reference clock comes from the quartz crystals used inside the PLL circuit. The sample frequency which the DAC works on can be set to: 44,1kHz, 48kHz, 88,2kHz, 96kHz, 176,4kHz, 192kHz while the bit resolution is always set to 24bits. The parameters of the mode are set in the dedicated menu option.
High performance power supply with two transformers (one of which toroidal) and eight different voltage regulation sections.
High-performance 192KHz/24bit D/A converter. The Over-Sampling of the DAC is present in all configurations and allows the use of low slope filters.
Low-jitter, sample-rate converter.
PLL implemented by discrete components.
Analogical circuits implemented by discrete components.
Highest-quality passive components: lowest-tolerance metallic-layered resistors (MIL standard),
Low-tolerance, non-polarized polyester/polypropylene capacitors.
High-speed, low-loss, high-capacity electrolytic capacitors and organic-electrolyte, low-capacity electrolytic capacitors.
High-contrast VFD graphic display.
Microcontroller system control.
THD @ 1KHz 0dBFs
THD @ 1KHz -10dBFs
135 x 445 x 395 mm
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